(1) Field of the Invention
The invention relates to oscillators. More specifically, the invention relates to duty cycle tuning for oscillator circuits.
(2) Background
Clock circuits are an essential component of modern computer systems. These circuits generate a regular series of pulses based on a piezoelectric crystal, which governs the frequency of the pulses. The clock signal that is generated is used to synchronize the operation of the other components and circuits in the system. For example, on a conventional motherboard for a personal computer a real time clock (RTC) and crystal oscillator circuit reside on the mother board to provide an consistent oscillating output signal to be used as the main clock by motherboard components such as an I/O controller hub (also known as a xe2x80x9csouth-bridgexe2x80x9d). A clock signal can be divided or multiplied to get seconds, minutes and hours to be used by a system for tracking the actual time (e.g., 7:05 am Dec. 21, 2002).
A crystal oscillator circuit generates sinusoidal oscillations across an LC tank, which are converted into a square waveform (i.e., clock signal), often using a biased analog inverter (i.e., a sine-to-square wave converter). This inverter trips at a designed trip point and the resulting duty cycle (the period during the clock cycle that the clock signal is xe2x80x98highxe2x80x99) of the generated clock signal is highly dependent on the trip point and the amplitude of the input waveform. During the start-up of a system, oscillations across a crystal slowly develop and continue to grow in amplitude until they reach a steady state (e.g., a constant amplitude). This start-up process often takes from several hundred milliseconds to a few seconds. The time needed to reach a steady state is determined by the crystal characteristics such as manufacturing variations, crystal type and the properties of an associated amplifier circuit. This start-up process in terms of computing time involves a considerable delay. Also, this start-up process often results in the generation of unreliable clock signals during the time before a steady state is obtained. This requires that circuits and components that rely on the clock signal must be designed to ignore clock signals during this initial period or otherwise shielded from these unreliable signals. For example, an RTC is often used as a system reference clock for a south-bridge. The south-bridge requires a clock signal having a duty cycle that is greater than 30% (i.e., the clock signal is high for at least 30% of a given cycle) from the time the south-bridge is powered on. However, because the use of all crystal oscillators involves a start-up process that results in the generation of unreliable clock signals the south-bridge must employ circuitry to filter out the clock signals during this period. Clock pulses generated by the sine-to-square wave converter during start-up may have a duty cycle as low as 0.01%. These runt clock pulses may place the logic state machines of a component like the south-bridge into a state of meta-stability, which is a state where a circuit fluctuates between logic states and ultimately results in an undeterminable logic state. One solution to avoid meta-stability problems is for components that rely on a system clock to xe2x80x98countxe2x80x99 for a predetermined time period after start before accepting the clock signal for use in logic state machines. This solution requires that components relying on the clock signal have special circuitry to implement this count. This makes the circuits larger, more complex and more costly.
The boot up operation of a computer system is reliant upon the establishment of a reliable system clock. Establishing this reliable signal adds additional time to the boot up process for a system. Also, for systems that switch between a low power and high power state such as personal computers, laptops, and hand held devices having to reestablish a reliable clock signal diminishes the responsiveness of the system.
Even when a clock signal has been established in a steady state, the resulting duty cycle cannot be predicted. The inability to predict or control a resulting duty cycle requires that logic state machines be designed to operate within a range of duty cycle times that cover the error margin for the duty cycle of an oscillator circuit. This requires the logic state machines to have additional circuitry to compensate for shortened or lengthened duty cycles.